This application claims priority to Korean Patent Application No. 2002-70684, filed on Nov. 14, 2002, in the Korean Intellectual Property Office, the disclosure of which is herein incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having an L-shaped spacer.
2. Description of the Related Art
Typically, a spacer of a semiconductor device is formed along the sidewalls of a gate electrode. The spacer is used as an implant mask to form a source/drain region and to electrically isolate the gate electrode from the source/drain region.
FIGS. 1 through 5 are illustrations depicting a conventional method of fabricating a semiconductor device having an L-shaped spacer.
Referring to FIG. 1, a gate insulating layer 33 is formed on a semiconductor substrate 31, such as a silicon substrate. A gate electrode 32 is formed on the gate insulating layer 33. The gate insulating layer 33 is formed of oxide or nitride, and the gate electrode 32 is formed of polysilicon. A first insulating layer 48 is formed on the semiconductor substrate 31 and the gate electrode 32. The first insulating layer 48 is formed of oxide. A shallowly doped source region 34 and a shallowly doped drain region 35 are formed in the semiconductor substrate 31. The shallowly doped source region 34 and the shallowly doped drain region 35 are formed by implanting impurities over the surface of the semiconductor substrate 31, where the gate electrode 32 and the first insulating layer 48 are formed. The shallowly doped source region 34 and the shallowly doped drain region 35 are aligned to the sidewalls of the gate electrode 32, wherein the gate electrode 32 prevents a portion of the underlying substrate 31 from being doped.
Referring to FIG. 2, a second insulating layer 36 and a third insulating layer 37, which are to be used as a spacer, are formed on the first insulating layer 48. The second insulating layer 36 is formed of nitride, and the third insulating layer 37 is formed of oxide.
Referring to FIG. 3, the third insulating layer 37 is anisotropically etched to form a first spacer 37 adjacent to the sidewalls of the gate electrode 32. Here, the second insulating layer 36 on an upper portion of the source region 34, the drain region 35, and the gate electrode 32 is exposed as indicated by reference numerals 38, 39, and 40.
Referring to FIG. 4, the second insulating layer 36 on the upper portion of the source region 34, the drain region 35, and the gate electrode 32, as indicated by reference numerals 38, 39, and 30, is etched to form a second spacer 36 at sidewalls of is the gate electrode 32. The second insulating layer 36 is wet etched by using phosphoric acid, and a portion of the second insulating layer 36, which is masked by the first spacer 37 and the first insulating layer 48, is not etched. Impurities are implanted on the surface of the semiconductor substrate 31. The first spacer 37 and the second spacer 36 function as a mask, and a deeply doped source region 43 and a deeply doped drain region 44 are formed by annealing the semiconductor device. Thus, a source extension and a drain extension are formed by the shallowly doped source region 34 and the shallowly doped drain region 35, respectively. The shallowly doped source region 34 and the shallowly doped drain region 35 are formed adjacent to the deeply doped source region 43 and the deeply doped drain region 44.
Referring to FIG. 5, the first spacer 37 and a portion of the first insulating layer 48 are removed. The portion of the first insulating layer 48 is on an upper portion of the deeply doped source region 43, an upper portion of the deeply doped drain region 44, and an upper portion of the gate electrode 32, as indicated by reference numerals 38, 39, and 40. The portion of the first insulating layer 48 is removed by a hydrofluoric (HF) acid etch. The gate electrode 32, the deeply doped source region 43, and the deeply doped drain region 44 are exposed. Silicide contacts 45, 46, and 47 are formed on the deeply doped source region 43, the gate electrode 32, and the deeply doped drain region 44.
According to the conventional method of fabricating a semiconductor device, impurities of the shallowly doped source region 34 and the shallowly doped drain region 35 are diffused when the annealing process is performed to form the deeply doped source region 43 and the deeply doped drain region 35. As a result of the diffused impurities, a short channel effect occurs in a highly-integrated semiconductor device.
Therefore, a need exists for a method of fabricating a semiconductor device having an L-shaped spacer that is capable of preventing a short channel effect from occurring.